RISC-V, a major project that seeks to facilitate open-source design for computer chips, is moving towards a formal release. Researchers at Princeton University, however, have discovered a series of errors in the instruction specification of RISC-V.
The researchers discovered about 100 errors of false orderings in the storage and retrieval of information from memory in variations of the RISC-V processor architecture. The researchers warned that the problems would high likely cause errors in software running on RISC-V chips if left uncorrected.
"Incorrect memory access orderings can result in software performing calculations using the wrong values," said Margaret Martonosi, the leader of the Princeton team. "These [RISC-V processors] in turn can lead to hard-to-debug software errors that either cause the software to crash or to be vulnerable to security exploits."
The errors were discovered while Martonosi's team was testing their new system to check memory operations across any computer architecture, according to Science Daily. The RISC-V project error has challenged the typical conformity to high-level program's assumptions, which now brings up a need to recheck all underlying instruction set for all types of processor design.
Daniel Lustig, co-researcher and a research scientist at NVIDIA, said that Martonosi's team is currently improving the RISC-V memory model. "RISC-V is in the fortunate position of being able to look back on decades' worth of industry and academic experience. It will be able to learn from all of the insights and mistakes made by previous attempts," he said.
Essentially, the RISC-V project enlists specifications, titled the Instruction Set Architecture, that guide the hardware and software design of RISC-V processors and software applications. According to Princeton Uni, the specifications and the instruction set enables hardware designers use basic information of the processor in building new chips, as well as computer programmers when writing new software.
